1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems having a functional circuit with an associated test wrapper circuit both containing latches with associated reset inputs.
2. Description of the Prior Art
It is known to provide test methodologies which utilise a test wrapper circuit comprising a plurality of test latches surrounding a functional circuit block within a larger integrated circuit. As an example, the functional circuit block may be a processor core which forms part of a system-on-chip design comprising several other circuit elements or blocks. The test wrapper allows test signals to be applied to the processor core to check it for correct operation and also allows test signals to be driven from the test wrapper surrounding the functional circuit to other elements within the system-on-chip design during an “extest” mode. This type of test methodology is the subject of the IEEE Standard P1500 which is currently under discussion.
As system-on-chip designs become larger and more complicated, the power consumption of such devices during testing can become a problem. More particularly, in their normal functional mode of operation the power consumption may be significantly below the power consumption which can occur during testing as during testing the circuits adopt states which would not normally occur during the functional mode. If the power supply of the design has been provided to meet the requirements of the functional mode, it may be that it is insufficient to properly meet the power requirements during testing and this can lead to erroneous test results and/possible circuit damage. Accordingly, measures which can allow the power consumption of a design to be reduced when it is being tested are advantageous.
One way of reducing power consumption during test is to disable operation of one or more functional blocks of circuitry not required to be active during certain tests, e.g. through clock gating and the like. However, in complicated designs clock gating can often introduce significant complications in the timing of the circuits and is undesirable in functional mode operation. This overrides its usefulness during testing. However, if a functional block of circuitry can be disabled in a manner that reduces its power consumption, it is possible for its associated test wrapper circuit to be used in an extest mode to generate output signals that are applied to other circuits within the design simulating the signals that would be generated by the disabled functional block of circuitry during functional mode operation.
Another design consideration for systems incorporating test wrapper circuits is that the circuit area overhead associated with the test wrapper should desirably be small. One way of helping to achieve this is to reuse latches that are part of the functional circuitry to also serve as latches within the test wrapper circuitry.